Course details of CS 226 - Digital Logic Design

Course Name Digital Logic Design
Total Credits 6
Type T
Lecture 3
Tutorial 0
Practical 0
Selfstudy 0
Half Semester N
Prerequisite
Text Reference M R Bhujade, Digital Computer Design Principles, 3rd Edition, Pitambar 1995. S H Unger, Essence of Logic Circuits, Prentice Hall, 1989. Zwi Kohavi, Switching and Finite Automata Theory, McGraw Hill, 1986. M R Bhujade, Introduction to VHDL: Lecture Notes, Department of Computer Science & Engineering, IIT,Mumbai,1998.M R Bhujade: Linear machines, Lectures notes on linear machines, Dept of computer science and Engineering, IIT Bombay, 2003,
Description Introduction : The nature of logic, Boolean Algebra and switching functions, Number Systems, binary, hexadecimal and other systems. Switching functions: Representation and properties of switching functions and their logic realizations using GATES and Switches. simplification of switching functions.Introduction to VHDL: Introduction to CAD for logic design, concepts of behavioral and structural description, Introduction to CAD tools, VHDL language concepts and statements. CAD of logic circuits through VHDL and FPGAs, CPLDs. Digital Systems Building blocks: Combinational logic elements, Decoders/Encoder, Multiplexors,De-multiplexors, Sequential logic elements, Flip-Flops, Registers, Shift Registers and Counters. Examples of applications. Optimal Design : Minterms and maxterms, canonical forms, cubes and subcubes, implicants and prime implicants, Minimization using K-map, Quine-McCluskey algorithm for finding prime implicants, selection of Prime implicants for a minimal expression using PI charts. Hazards in combinational circuits. Finite State machines(FSMs): Synchronous, asynchronous and pulse mode models,mealy and Moore machines. State diagrams, state tables, state assignment and synthesis using D,JK and T flip flops. State minimization for completely and incompletely specified machines. Primitive flow table, state minimization and reduced flow table. state assignment and Races in asynchronous circuits, Race free state assignments Error detection and correction: Errors in fixed length messages and their detection using parity checks. Correction through hamming codes. Errors in variable length messages and polynomial codes (cyclic codes) error detection properties of polynomials and burst error detection.Implementation using linear machines.
Last Update 28-04-2016 14:55:27.673622