Three-Day CEP Course by
Indian
Institute of Technology Bombay
and
Electronics
Regional Test Laboratory (ERTL)-Mumbai
ELECTROMAGNETIC
INTERFERENCE AND ELECTROMAGNETIC COMPATIBILITY IN ELECTRONIC AND POWER
ELECTRONIC SYSTEMS
January 12 – 14, 2003
INTRODUCTION
Electromagnetic-Interference
(EMI) is an undesired electrical signal within the elements of a circuit, which
is produced by coupling from another signal external to the circuit or from
elsewhere in the circuit. EMI was earlier a phenomenon observed mostly in
communication systems, but is now associated with telecommunication equipment,
computers and all sorts of electronic, and power electronic systems. The
problem has been complicated due to the advent of high-speed semi-conductor
devices and the growth of VLSI circuits. High component and PCB trace densities
have also contributed to this problem. EMI problem is further compounded due to
the introduction of intelligent systems in power product categories such as
UPS, home appliance and comfort systems. It is desirable that electronic
circuits do not radiate undesired signals as well as they are compatible with
the environment in which they work (EMC). This course aims at highlighting the
evils of EMI, how to measure and analyze EMI and how to minimize it.
APPLICATIONS
The course
has applications basically in electrical, electronic and power electronic
system design, PCB design and VLSI systems etc.
The CE Mark
COURSE OUTLINE
1)
Basic EMI/EMC
concepts (conducted or radiated EMI, EMI sources, Coupling modes, Crosstalk
propagation, far field, near field, harmonics, etc.)
2)
EMI/EMC
Standards, European Union EMC Directive and CE marking.
3)
Grounding/filtering/shielding/screening
and
surge protection/suppression - both the aspects – that of noise suppression at
the source and noise coupled to the system will be considered.
4)
PCB design
aspects(layouts, layers, etc.) from EMI point of view
5)
EMI measuring
and testing instruments (Spectrum Analyzer, LISN, EFT etc.)
6)
Case studies
of EMI in actual systems
7)
Demos:
a.
Conducted EMI
in switched mode power supplies (SMPS)
b.
Noise due to
ESD
c.
Immunity test
of conducted and radiated origin
d.
Crosstalk
between cables and PCB traces
e.
Miscellaneous
examples
COURSE STRUCTURE
The course consists
of two major components: lectures and lab demonstrations. Lectures will
generally be held in the morning sessions & demos in the afternoon
sessions. The demonstrations will
provide an opportunity to the participants to discuss their difficulties on
ideas and applications presented in the lectures. Course material based on the
lectures will be made available at the time of the course.
WHO MAY BENEFIT
Design Engineers
working with electrical and electronic circuits, systems and their packaging,
PCB Designers, QA Personnel and marketing executives.
VENUE
·
Conference
Room, Ist Floor, Opp. EE office, Dept. of Electrical Engg., IIT Bombay.
(Kindly report here for
registraton on 12-1-03)
·
ERTL, opp.
SEEPZ, MIDC, Mumbai.
COURSE
DATE & TIMINGS
January
12 – 14, 2003. 9.00 A.M. - 6.00 P.M.
COURSE
FEE
The
course fee is Rs. 5000/- for participants from industry and Rs. 3000/- for
participants from Academic Institutions and R&D organisations (to produce a
letter from the institution).
LODGING
AND BOARDING
Accommodation
in the Institute Guest House is available for a limited number of participants
on paid basis and with advance request.
REGISTRATION
Fill out the attached Registration form and mail it
along with the course fees to the course coordinator. Fees must be paid by a
demand draft drawn in favour of "REGISTRAR, IIT BOMBAY - CEP A/C”.
Kindly
note that no income tax is to be deducted at source from the course fee
payments as IIT Bombay is exempted from the same.
Deadline for Registration: December 24, ‘02
Please
address all communication to:
Dr. Vivek Agarwal, (Course Coordinator)
Department of
Electrical Engineering,
Indian Institute of
Technology, Bombay
Mumbai 400 076
Phone : 022-2576-7422
Fax : 022-2572-3707
Email : agarwal@ee.iitb.ac.in
REGISTRATION FORM
Three-Day CEP Course On
Electromagnetic Interference and
Electromagnetic Compatibility
In Electronic and Power Electronic Systems
January 12-14,
2003
NAME (PRINT) :
__________________________________________________________________
_______________________________________Gender:
M / F Age: ___Yrs.
DESIGNATION : __________________________________________________
ORGANIZATION:
_________________________________________________________________
MAILING ADDRESS :
_______________________________________________
_________________________________________________________________
_________________________________________________________________
TELEPHONE
:_________________________ FAX:
______________________
EMAIL :
__________________________________________________________
Qualification (highest degree)
:________________________________________
Discipline :____________________________ EXPERIENCE : _________ Yrs.
PAYMENT: D.D. No.: Dt. Rs.
(DD in favour of Registrar, IIT Bombay – CEP a/c )
Academic Research Institution Certificate
Attached : YES / NO
IIT Guest House
accommodation required? : YES / NO
(Guest
House bill to be paid directly by participant.)
Date: Signature of
Applicant
(PHOTOCOPY
ADDITIONAL COPIES IF NEEDED)
(Please feel free to make copies of this announcement and distribute it to others having interest in EMI/EMC).